I²C Pull-Up Resistor Calculator

There is no single right pull-up — there is a window. Enter the supply, bus speed and bus capacitance to get the range that works and the standard values inside it.

How it works

Too large a resistor and the bus capacitance makes the rising edge too slow. Too small and a device cannot pull the line low enough.

• R_max = t_r / (0.8473 · C_b) — the spec measures rise time from 30% to 70% of VDD, and an RC edge takes ln(0.7/0.3) = 0.8473·RC to do that. t_r = 1000 ns (100 kHz), 300 ns (400 kHz), 120 ns (1 MHz).
• R_min = (VDD − V_OL) / I_OL — I_OL = 3 mA (Standard and Fast), 20 mA (Fast-mode Plus). V_OL = 0.4 V, or 0.2·VDD when VDD is 2 V or less.

Pick a standard value inside the window, nearer the low end for rise-time margin. If the window is closed: lower the speed, split the bus, cut the capacitance, or use a bus buffer or an active pull-up.

Worked example

3.3 V, 400 kHz, 200 pF. R_max = 300 ns / (0.8473 × 200 pF) ≈ 1.77 kΩ. R_min = (3.3 − 0.4) V / 3 mA ≈ 967 Ω. So 1.0–1.6 kΩ works — 1.2 kΩ is a good choice. The "always 4.7 kΩ" habit fails here: 4.7 kΩ × 200 pF × 0.8473 ≈ 800 ns, far over the 300 ns limit.

Assumptions

• One pull-up per line. If several boards each add their own, they are in parallel — count them all.
• No series resistors, no leakage, no current-source pull-ups.
• Bus capacitance limit: 400 pF (Standard, Fast), 550 pF (Fast-mode Plus). The tool warns above that.
• Results are for learning and first sizing — confirm on the bench with a scope (30–70% rise time).

Sources

• NXP UM10204, I²C-bus specification and user manual — rise-time limits, V_OL/I_OL and the pull-up sizing formulas.
• Check your devices' datasheets: V_OL, I_OL and pin capacitance vary from part to part.

Tool v1.1 · 15 Nov 2026 · formulas checked by 28 automated tests.

The interview question behind this tool

EM-02 — Sizing I²C pull-ups (free full answer) · EM-01 — I²C vs SPI (free full answer)